PDF Virtual Prototyping of Parallel and Embedded Systems
The Workshop on Virtual Prototyping of Parallel and Embedded Systems ViPES is an annual workshop and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing.
This special issue of ACM Transactions on Embedded Computing Systems (ACM TECS) invites authors who presented their work at the VIPES workshop, as well as all researchers who work in the area of Virtual Prototyping.
Virtual prototyping stands for the development of hardware/software systems without using a real hardware prototype, i.e. no printed circuit board with electronic devices such as processors, field programmable gate arrays, peripherals and other devices is needed. The advantage is the possibility to exchange parts in the system setup with faster turnaround times in comparison with the traditional development process, where a time consuming redesign of the complete board has to be done. Since some years, the community exploiting these novel methods has grown as time to market plays a major role in industry. Additionally, the increasing complexity of embedded systems, which are more and more realized as parallel and distributed cyber-physical system, forces to perform a time-consuming design space exploration. For academics virtual prototyping is a hot topic and is used to develop future systems and to enable an outlook into the next generation of embedded systems and devices. The wide range of application scenarios for this type of development includes amongst others automotive, avionics, railway and medicine applications.
This special issue targets the domain of virtual prototyping focusing the following topics:
- Virtual prototyping development tools
- Methods for virtual prototyping of complex systems
- Application development with virtual platforms
- Methods for Hardware / Software Codesign with virtual platforms
- Design space exploration for parallel and distributed multicore and cyber-physical systems
- Estimation of system characteristics in an early stage of development
- Functional verification at a high level of abstraction
- Methods for modeling of IP cores with SystemC
- Usage of Architecture Description Languages (ADL) for IP–core development
Consideration for publication elsewhere. Conference papers may only be submitted if the paper was completely re-written or substantially extended (30%). The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TECS formatting requirements. The page count limit is 25.
Authors should submit their journal version at Manuscript Central adhering to the formatting instructions on the TECS Web page and indicate that you are submitting to the Special Issue on Application of Concurrency to System Design on the first page and in the field "Author's Cover Letter:" in Manuscript Central. For additional questions please send an email Jeronimo Castrillon.